`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/11/05 17:44:45
// Design Name: 
// Module Name: four_bit_lookforward_fulladd
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module four_bit_lookforward_fulladd(A,B,CI,S,CO);
  input [3:0] A,B;
  input CI;
  output CO;
  output [3:0] S;
  
  wire [3:0] g,p;
  wire [4:1] c;
  generator
   G1(A[0],B[0],CI,g[0],p[0],S[0]),
   G2(A[1],B[1],c[1],g[1],p[1],S[1]),
   G3(A[2],B[2],c[2],g[2],p[2],S[2]),
   G4(A[3],B[3],c[3],g[3],p[3],S[3]);
   
  four_bit_CLA
   CLA(p,g,CI,c);
 
  assign CO=c[4];
endmodule
